1. Field of the Invention
The present invention relates to a pillar-shaped semiconductor memory device including memory elements formed around a pillar-shaped semiconductor, and a method for producing the device.
2. Description of the Related Art
In recent years, electronic devices using a memory device typified by flash memory have been used in various fields, and the application fields and the market size of the devices have been increasingly expanding. With these circumstances, the realization of highly integrated memory devices and a reduction in the cost of the memory devices have been desired.
NAND-type flash memory is advantageous in terms of the degree of integration and cost thereof (for example, F. Masuoka, M. Momotomi, Y. Iwata, and R. Shirota: “New ultra high density EPROM and Flash EEPROM with NAND structured cell”, IEDM Tech. Dig. pp. 552-555 (1987)). Japanese Unexamined Patent Application Publication No. 4-79369 (Patent Literature 1) discloses, as highly integrated NAND-type flash memory, a vertical NAND flash memory device including a plurality of memory cell-transistors stacked on a semiconductor silicon pillar (hereinafter, a semiconductor silicon pillar is referred to as “Si pillar”) in a direction in which the Si pillar stands.
The vertical NAND flash memory device disclosed in Patent Literature 1 will be described with reference to FIG. 6. FIG. 6 illustrates a sectional structure of the vertical NAND flash memory device disclosed in Patent Literature 1. Silicon (Si) pillars 101a and 101b are formed on an intrinsic semiconductor silicon substrate 100 (hereinafter, an intrinsic semiconductor silicon substrate is referred to as “i-layer substrate”). Silicon dioxide (SiO2) layers 102a and 102b which are tunnel insulating layers are formed so as to surround outer peripheral portions of the Si pillars 101a and 101b, respectively. Floating electrodes 103a and 103b that electrically float are formed so as to surround outer peripheral portions of the SiO2 layers 102a and 102b, respectively. Source-side selection gate electrodes 104a and 104b are formed around lower portions of the Si pillars 101a and 101b, respectively. Drain-side selection gate electrodes 105a and 105b are formed around upper portions of the Si pillars 101a and 101b, respectively. Interlayer SiO2 layers 107a and 107b are formed so as to surround outer peripheries of the floating electrodes 103a and 103b, respectively. Word-line electrodes 108a and 108b are formed so as to surround outer peripheries of the interlayer SiO2 layers 107a and 107b, respectively. A common source N+ layer 109 (hereinafter, a semiconductor layer containing a donor impurity in a large amount is referred to as “N+ layer”) is formed in a surface layer of the i-layer substrate 100, the surface layer extending to bottom portions of the Si pillars 101a and 101b. Drain N+ layers 110a and 110b are formed in top portions of the Si pillars 101a and 101b, respectively. A SiO2 layer 111 is further formed by chemical vapor deposition (CVD) so as to cover the whole surface. Bit-line wiring metal layers 113a and 113b are respectively formed through contact holes 112a and 112b formed on the drain N+ layers 110a and 110b, respectively. Furthermore, P− layers 114a and 114b (hereinafter, a semiconductor layer containing an acceptor impurity in a small amount is referred to as “P− layer”) are respectively formed in the Si pillars 101a and 101b on the i-layer substrate 100. Memory cell-transistors Qc1 include the SiO2 layers 102a and 102b, the floating electrodes 103a and 103b, the interlayer SiO2 layers 107a and 107b, and the word-line electrodes 108a and 108b, all of which are formed so as to surround outer peripheral portions of the P− layers 114a and 114b in the Si pillars 101a and 101b, respectively. Memory cell-transistors Qc2 and Qc3 that have the same structures as the memory cell-transistors Qc1 are formed on the Si pillars 101a and 101b. The memory cell-transistors Qc1, Qc2, and Qc3 are electrically insulated from each other. The memory cell-transistors Qc1, Qc2, and Qc3 are stacked in a direction in which the Si pillars 101a and 101b stand. Furthermore, source-side selection transistors Qs1 having the source-side selection gate electrodes 104a and 104b are formed below the memory cell-transistors Qc1, Qc2, and Qc3. Drain-side selection transistors Qs2 having the drain-side selection gate electrodes 105a and 105b are formed above the memory cell-transistors Qc1, Qc2, and Qc3.
In producing the vertical NAND flash memory device disclosed in Patent Literature 1, the SiO2 layers 102a and 102b which are tunnel insulating layers, the interlayer SiO2 layers 107a and 107b, the source-side selection gate electrodes 104a and 104b, the drain-side selection gate electrodes 105a and 105b, the floating electrodes 103a and 103b, and the word-line electrodes 108a and 108b are formed so as to surround outer peripheral portions of the Si pillars 101a and 101b, respectively. In this case, it is difficult to form these layers and electrodes so as to have less defects and high reliability.
A possible higher-density vertical NAND flash memory device is a NAND-type flash memory device including two NAND-type flash memory elements formed on a single Si pillar.
An example of such a NAND-type flash memory device will be described with reference to FIGS. 7A and 7B. FIG. 7A is a schematic view of a three-dimensional structure of a NAND-type flash memory device, and FIG. 7B is a schematic view of a sectional structure of the NAND-type flash memory device. A tunnel insulating layer 122 is formed so as to surround a Si pillar 120. A plurality of first floating electrodes FGa1, FGa2, and FGan and a plurality of second floating electrodes FGb1, FGb2, and FGbn are formed on outer peripheral portions of the tunnel insulating layer 122 so as to be arranged in a direction in which the Si pillar 120 stands. The first floating electrodes FGa1, FGa2, and FGan and the corresponding second floating electrodes FGb1, FGb2, and FGbn are disposed at the same height in the direction in which the Si pillar 120 stands, and isolated from each other. An interlayer insulating layer 125 is formed so as to surround the first floating electrodes FGa1, FGa2, and FGan and the second floating electrodes FGb1, FGb2, and FGbn. First control electrodes CGa1, CGa2, and CGan are respectively formed on the first floating electrodes FGa1, FGa2, and FGan with the interlayer insulating layer 125 therebetween. Second control electrodes CGb1, CGb2, and CGbn are respectively formed on the second floating electrodes FGb1, FGb2, and FGbn with the interlayer insulating layer 125 therebetween. The first control electrodes CGa1, CGa2, and CGan and the corresponding second control electrodes CGb1, CGb2, and CGbn are disposed at the same height in the direction in which the Si pillar 120 stands, and isolated from each other. A gate insulating layer 123a is formed, so as to surround the Si pillar 120, in contact with the tunnel insulating layer 122 and below the tunnel insulating layer 122 in the direction in which the Si pillar 120 stands. A source-side selection electrode 124a is formed so as to surround the gate insulating layer 123a. A gate insulating layer 123b is formed, so as to surround the Si pillar 120, in contact with the tunnel insulating layer 122 and above the tunnel insulating layer 122 in the direction in which the Si pillar 120 stands. A drain-side selection electrode 124b is formed so as to surround the gate insulating layer 123b. A source N+ layer 121a is formed in a bottom portion of the Si pillar 120. A drain N+ layer 121b is formed in a top portion of the Si pillar 120. The first control electrodes CGa1, CGa2, and CGan are connected to first word-line wring layers WLa1, WLa2, and WLan, respectively. The second control electrodes CGb1, CGb2, and CGbn are connected to second word-line wring layers WLb1, WLb2, and WLbn, respectively. The first word-line wring layers WLa1, WLa2, and WLan and the second word-line wring layers WLb1, WLb2, and WLbn are driven electrically independently. The Si pillar 120 functioning as a channel, the gate insulating layer 123b, and the drain-side selection electrode 124b form a drain-side selection transistor. The Si pillar 120 functioning as a channel, the gate insulating layer 123a, and the source-side selection electrode 124a form a source-side selection transistor. The source-side selection electrode 124a is connected to a source-side selection gate line SGSa. The drain-side selection electrode 124b is connected to a drain-side selection gate line SGDa. The source N+ layer 121a is connected to a common source line CSLa. The drain N+ layer 121b is connected to a bit-line wiring BLa.
According to the vertical NAND flash memory device illustrated in FIGS. 7A and 7B, a first NAND-type flash memory element and a second NAND-type flash memory element are formed on the single Si pillar 120. The first NAND-type flash memory element and the second NAND-type flash memory element share the source N+ layer 121a, the drain N+ layer 121b, the source-side selection transistor, and the drain-side selection transistor. The first NAND-type flash memory element includes, as a channel, a surface layer portion of the Si pillar 120 facing the first control electrodes CGa1, CGa2, and CGan. The second NAND-type flash memory element includes, as a channel, a surface layer portion of the Si pillar 120 facing the second control electrodes CGb1, CGb2, and CGbn.
In producing the vertical NAND flash memory device illustrated in FIGS. 7A and 7B, the tunnel insulating layer (SiO2 layer) 122, the interlayer insulating layer (interlayer SiO2 layer) 125, the source-side selection electrode 124a, the drain-side selection electrode 124b, the first floating electrodes FGa1, FGa2, and FGan, the second floating electrodes FGb1, FGb2, and FGbn, the first control electrodes CGa1, CGa2, and CGan, and the second control electrodes CGb1, CGb2, and CGbn are formed so as to surround outer peripheral portions of the Si pillar 120. Also in this case, it is difficult to form these layers and electrodes so as to have less defects and high reliability. Furthermore, in this vertical NAND flash memory device, a reliable operation is desired for the two NAND-type flash memory elements connected in parallel.
Japanese Unexamined Patent Application Publication No. 2011-165815 (Patent Literature 2) discloses a method for producing a semiconductor memory device, the method including repeatedly stacking a word-line electrode material layer and an insulating layer on a substrate, forming a through-hole passing through the resulting stacked word-line conductor layers and the interlayer insulating layers, forming an interlayer insulator layer, a data charge storage layer that stores data charges, and a tunnel insulating layer on a surface layer of the side surface of the through-hole, further filling the through-hole with a poly-Si layer (hereinafter, a polycrystalline Si layer is referred to as “poly-Si layer”) functioning as a channel, and forming two NAND-type flash memory elements including the poly-Si layer as channels.
The method for producing a semiconductor memory device disclosed in Patent Literature 2 will be described with reference to FIG. 8. FIG. 8 is a plan view of a semiconductor memory device including word-line conductor layers disposed on two sides of an outer peripheral portion of a semiconductor pillar, and two NAND-type flash memory elements that are formed on two semiconductor pillars in a connecting manner. First, material layers each including, as one set, a conductor layer functioning as a word line, and an insulating layer formed on the conductor layer are stacked in a vertical direction in plan view to form a stacked material layer (not illustrated). Next, a circular hole Tc having a circular shape in plan view and a rectangular hole Ts connected to the circular hole Tc, the circular hole Tc and the rectangular hole Ts penetrating through the stacked material layer, are formed (the whole of the circular hole Tc and the rectangular hole Ts are referred to as “through-hole T”). Next, an interlayer insulating layer 130 formed of, for example, a SiO2 layer is formed in the through-hole T. The interlayer insulating layer 130 includes an interlayer insulating layer 130a in the circular hole Tc and an interlayer insulating layer 130b in the rectangular hole Ts. The side surface of the circular hole Tc is covered with the interlayer insulating layer 130a. The whole of the rectangular hole Ts is filled with the interlayer insulating layer 130b. Next, a data charge storage layer 131 formed of, for example, a Si3N4 layer (silicon nitride layer) is formed on the inner side surface of the interlayer insulating layer 130a in the circular hole Tc. Next, a tunnel insulating layer 132 formed of, for example, a SiO2 layer is formed on the inner side surface of the data charge storage layer 131. Next, the through-hole surrounded by the tunnel insulating layer 132 is filled with, for example, poly-Si to form semiconductor pillars Pa and Pb. Next, the stacked material layer in a region 135 disposed between the semiconductor pillars Pa and Pb is removed by etching. As a result, a conductor layer CGa and a conductor layer CGb that function as word lines and that are isolated on two sides of the semiconductor pillars Pa and Pb in the Y direction are formed. Next, a common source diffusion layer and a source-side selection transistor are formed in a top portion of each of the semiconductor pillars Pa. A drain diffusion layer and a drain-side selection transistor are formed in a top portion of each of the semiconductor pillar Pb. A connecting portion that connects the channel of the semiconductor pillar Pa and the channel of the semiconductor pillar Pb is formed in a bottom portion of the semiconductor pillars Pa and Pb. This structure provides a semiconductor memory device including two NAND-type flash memory elements which have independent channels on surface layers of the semiconductor pillars Pa and Pb on the left and the right in the Y direction, in which when one of the elements is controlled by the word-line conductor layer CGa, the other is controlled by the word-line conductor layer CGb, and which are connected to the semiconductor pillars Pa and Pb.
In the formation of the through-hole T in the semiconductor memory device illustrated in FIG. 8, a width La of the rectangular hole Ts in the Y direction needs to be smaller than a diameter Lb of the circular hole Tc. The reason for this is to make the outer perimeter of the circular hole Tc disposed between the rectangular holes Is long as much as possible so as to increase the area of the channels of the semiconductor pillars Pa and Pb controlled by the word-line conductor layers CGa and CGb. With this structure, since a read-out current of the NAND-type flash memory elements can be increased, memory cell data can be easily read. The circular holes Tc and the rectangular holes Ts are formed at the same time using lithography and reactive ion etching (RIE). In this case, the width La in the Y direction is the minimum process dimension, and thus the diameter Lb of each of the circular holes Tc is larger than the width La. Therefore, it is necessary to form the circular holes Tc having a large diameter Lb in the Y direction, and thus the degree of integration of the flash memory elements may be decreased. Furthermore, in order to form the circular holes Tc by patterning with lithography so as to be adjacent to each other and to have a circular shape, it is necessary to form a gap between the circular holes Tc. Therefore, in the X direction, the rectangular holes Ts need to be formed between the circular holes Tc, and thus the degree of integration of the flash memory elements may be decreased. As described above, in both the X direction and the Y direction, there may be a problem in that the degree of integration of the flash memory elements is decreased by the presence of the rectangular holes Ts.
In addition, it is difficult to form the interlayer insulating layer 130a, the data charge storage layer 131, and the tunnel insulating layer 132 having less defects and high reliability on the surface layer of the side surface of the deep through-hole T. Furthermore, the channels of, for example, poly-Si semiconductor pillars Pa and Pb have a lower mobility and a larger trap level, which may cause an increase in the threshold voltage, compared with channels formed of single-crystal Si. Accordingly, a high read-out current is necessary, resulting in a difficulty in a low-voltage driving.